3d stacked multilayer semiconductor memory using doped select transistor channel

ABSTRACT

In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor.

BACKGROUND Field of the Invention

The present invention generally relates to 3D stacked multilayer semiconductor memories such as NAND and NOR memories.

Description of the Related Art

As 3D stacked multilayer semiconductor memories, several candidates have been pursued, including NAND and NOR memories. One approach is to utilize different types of semiconductors as stacking films. This method is beneficial in that a channel can be formed with a crystal semiconductor that enables much faster operation than a poly-Si channel that is constructed by stacking a poly-Si layer and a SiO layer. One example using such a crystal semiconductor is described in IEDM 2009, p 637-640, by A. Hubert et al. wherein a Si—SiGe stacked structure is utilized. Another example is described in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011, p 1006-1014, by Jan-Gn Yun et al. These two examples focus on NAND flash memories. Other applications including logic circuits are described in U.S. Pat. No. 8,581,349 B1. In stacking of multiple semiconductors such as those in the above examples, one issue to be worked on when using a select transistor is how to perform doping in a channel region of a select transistor because a doping concentration of the select transistor channel has to be different from that of a channel of a memory transistor. Another issue to be worked on when using a select transistor is how to establish isolation of the select transistor from the memory transistor. In conventional NAND and NOR memories, isolation is not needed because every memory transistor is aligned serial to each other, but a select transistor requires isolation from a memory transistor.

In an example of fabricating a select transistor that is compatible to memory transistor formation, multiple select transistors are formed for one select line (silicon layer), and by using a combination of ON and OFF states of these multiple select transistors, it is possible to define which line is selected. This technique is described in IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 7, JULY 2016, p 866-869. This technique does not require additional fabrication steps for select transistors, but requires changing a threshold voltage of each select transistor by injecting an electrical charge to a gate oxide of the select transistor prior to a reading cycle. Injecting an electrical charge to the gate oxide involves a disadvantage of deterioration in reading latency.

Any discussion of problems and solutions in relation to the related art has been included in this disclosure solely for the purposes of providing a context for the present invention, and should not be taken as an admission that any or all of the discussion was known at the time the invention was made.

SUMMARY

In view of the problems discussed above, according to an embodiment of the present invention, in 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor.

According to an embodiment of the present invention, the doped channel of the select transistor is formed as follows: A boron-doped film is formed in a region of stacked layers where the select transistor channel is to be formed, which stacked layers are constituted by heavily doped N-type semiconductor layers and lightly doped P-type (or undoped) semiconductor layers, wherein the heavily doped N-type semiconductor layers in the region are converted to lightly doped P-type semiconductor layers, and the lightly doped P-type (or undoped) semiconductor layers in the region are converted to heavily doped P-type semiconductor layers.

According to another embodiment of the present invention, the doped channel of the select transistor is formed as follows: A staircase is formed in a region of stacked layers where the select transistor channel is to be formed, which stacked layers are constituted by heavily doped N-type semiconductor layers and lightly doped P-type (or undoped) semiconductor layers, and then, boron is doped by ion implantation, wherein the heavily doped N-type semiconductor layers in the region are converted to lightly doped P-type semiconductor layers, and the lightly doped P-type (or undoped) semiconductor layers in the region are converted to heavily doped P-type semiconductor layers.

According to some embodiments, a suitable threshold voltage can be provided to a select transistor without deterioration of reading latency, and also proper isolation can be provided for selecting a memory transistor in a 3D stacked multilayer semiconductor memory.

For purposes of summarizing aspects of the invention and the advantages achieved over the related art, certain objects and advantages of the invention are described in this disclosure. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

Further aspects, features and advantages of this invention will become apparent from the detailed description which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will now be described with reference to the drawings of preferred embodiments which are intended to illustrate and not to limit the invention. The drawings are greatly simplified for illustrative purposes and are not necessarily to scale.

FIG. 1 illustrates schematic perspective views of a partially fabricated integrated memory array, showing boron-doping processes (a) and (b) according to an embodiment of the present invention.

FIG. 2 illustrates schematic perspective views of a partially fabricated integrated memory array, showing boron-doping processes (a) to (c) and wiring processes (d) and (e) according to an embodiment of the present invention.

FIG. 3 illustrates schematic perspective views of the partially fabricated integrated memory array illustrated in FIG. 2, showing array forming processes (a) to (d) according to an embodiment of the present invention.

FIG. 4 illustrates a schematic perspective view of fabricated integrated memory arrays according to an embodiment of the present invention.

FIG. 5 illustrates a schematic equivalent circuit of a fabricated 3D stacked multilayer semiconductor memory, showing writing operation according to an embodiment of the present invention.

FIG. 6 illustrates a schematic equivalent circuit of a fabricated 3D stacked multilayer semiconductor memory, showing reading operation according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Conventional 3D stacked multilayer semiconductor memories such as NAND and NOR flash memories are described in many documents such as Jang-Gn Yun, et al., “Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011, p 1006-1014; A. Hubert, et al., “A stacked SONOS technology, up to 4 levels and 6 nm crystalline nanowires, with gate-all-around or independent gates (φ-Flash), suitable for full 3D integration,” IEDM 2009, p 637-640; Sang-Ho Lee, et al., “Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory,” IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 7, JULY 2016, p 866-869; Kawamu Sakuma, et al., “Highly Scalable Horizontal Channel 3-D NAND Memory Excellent in Compatibility With Conventional Fabrication Technology,” IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013, pp 1142-1144; and U.S. Pat. No. 8,581,349 B1. In this disclosure, each disclosure of the above documents is incorporated herein by reference in its entirety to the extent that it is consistent with and applicable to this disclosure. In the present disclosure where conditions and/or structures are not specified, a skilled artisan in the art can readily provide such conditions and/or structures, in view of the present disclosure and other documents such as those identified above, as a matter of routine experimentation.

In some embodiments, “film” refers to a layer continuously extending in a direction perpendicular to a thickness direction substantially without pinholes to cover an entire target or concerned surface, or simply a layer covering a target or concerned surface. In some embodiments, “layer” refers to a structure having a certain thickness formed on a surface or a synonym of film or a non-film structure. A film or layer may be constituted by a discrete single film or layer having certain characteristics or multiple films or layers, and a boundary between adjacent films or layers may or may not be clear and may be established based on physical, chemical, and/or any other characteristics, formation processes or sequence, and/or functions or purposes of the adjacent films or layers. Further, in this disclosure, any two numbers of a variable can constitute a workable range of the variable as the workable range can be determined based on routine work, and any ranges indicated may include or exclude the endpoints. Additionally, any values of variables indicated (regardless of whether they are indicated with “about” or not) may refer to precise values or approximate values and include equivalents, and may refer to average, median, representative, majority, etc. in some embodiments. Further, in this disclosure, an article “a” or “an” refers to a species or a genus including multiple species, depending on the context. The terms “constituted by” and “having” refer independently to “typically or broadly comprising”, “comprising”, “consisting essentially of”, or “consisting of” in some embodiments. Further, in some embodiments, the structures may consist of required elements described in the present disclosure; however, “consist of” does not exclude additional components that are unrelated to the invention such as impurities ordinarily associated therewith. In some embodiments, any one or more elements described as alternative or optional element(s) in the present disclosure can explicitly be eliminated from the structures.

In all of the disclosed embodiments, any element used in an embodiment can be replaced with any elements equivalent thereto, including those explicitly, necessarily, or inherently disclosed herein, for the intended purposes.

In this disclosure, any defined meanings do not necessarily exclude ordinary and customary meanings in some embodiments.

Embodiments of the present invention will be explained with respect to preferred embodiments. However, the present invention is not limited to the preferred embodiments.

In an embodiment, a 3D stacked multilayer semiconductor memory comprises:

-   -   memory transistors constituted by heavily doped N-type         semiconductor layers and lightly doped or undoped P-type         semiconductor layers alternately layered with one another in a         stacking direction, each layer extending in a longitudinal         direction perpendicular to the stacking direction; and     -   select transistors constituted by lightly doped P-type         semiconductor layers and heavily doped P-type semiconductor         layers alternately layered with one another, said select         transistors being provided with gate electrodes,     -   wherein the lightly doped P-type semiconductor layers of the         select transistors are connected, continuously in the         longitudinal direction, to one ends of the heavily doped N-type         semiconductor layers of the memory transistors, respectively,         and the heavily doped P-type semiconductor layers of the select         transistors are connected, continuously in the longitudinal         direction, to one ends of the lightly doped or undoped P-type         semiconductor layers of the memory transistors, respectively,         and     -   wherein the lightly doped P-type semiconductor layers of the         select transistor function as channels to select one of the         heavily doped N-type semiconductor layers when applying voltage         to the gate electrodes, and the heavily doped P-type         semiconductor layers of the select transistors function as         isolators to isolate the heavily doped P-type semiconductor         layers from the lightly doped or undoped P-type semiconductor         layers of the memory transistors.

In the above embodiment, the select transistor is a MOS transistor (or MOSFET, Metal-Oxide-Semiconductor-Field-Effect-Transistor) which is configured to select a heavily doped N-type semiconductor layer (referred to also as “N+ layer”), whereas the string select transistor disclosed in IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 7, JULY 2016, p 866-869 or the transistor disclosed in U.S. Pat. No. 8,581,349 B1 (e.g., FIG. 70D) is configured to select a lightly doped or undoped P-type semiconductor layer. In a MOS transistor, a channel is formed under a gate, and in case of an nMOS transistor, the channel is constituted by a lightly doped or undoped P-type layer. In the above embodiment, the select transistor is oriented in a horizontal direction, whereas the memory transistor is oriented in a vertical direction. The select transistor includes, but is not limited to, a line select transistor, cut-off transistor, source select transistor, and any other select transistor having an equivalent function and structure.

According to the above configurations where the select transistor channel region connected to the memory transistor (i.e., word line transistor) has the structure where the lightly doped P-type semiconductor layer (referred to also as “P− layer”) is formed on top of the heavily doped P-type semiconductor layer (referred to also as “P+ layer”), a suitable threshold voltage for the select transistor can effectively be provided without deterioration of reading latency, because, unlike the 3D stacked NAND flash memory disclosed in IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 7, JULY 2016, p 866-869, for example, injecting an electrical charge to the select transistor is not required for reading, thereby increasing reading speed. In this embodiment, without injecting an electrical charge to the select transistor, by changing a dopant concentration in the channel of the select transistor, threshold voltage for the select transistor can be differentiated from that for the word line channel (the channel of the memory transistor).

Also, according to the above configurations, a proper isolation can effectively be established, which isolates the channel of the memory transistor (the lightly doped or undoped P-type semiconductor layer) from the select transistor, because the heavily doped P-type semiconductor layer of the select transistor functions as an isolator (because the heavily doped P-type semiconductor layer, i.e., the region of different dopant concentration, is disposed in the layer of the lightly doped or undoped P-type semiconductor layer).

In this disclosure, a “heavily doped” layer or the like typically refers to a layer containing the target element doped thereto totally at an atomic concentration of above 1×10¹⁹/cm³ or higher, preferably above 1×10²⁰/cm³ (which is the total concentration, regardless of how much the target element is doped by a particular doping process), and a “lightly doped” layer or the like typically refers to a layer containing the target element doped thereto totally at atomic concentration of less than about 1×10¹⁹/cm³ (which is the total concentration, regardless of how much the target element is doped by a particular doping process). Further, when a doped layer is doped with a donor (e.g., phosphorous or arsenic) and an acceptor (e.g., boron or aluminum), one of the donor and the acceptor is functionally dominant and the function of a part of the dominant element is offset or compromised by that of the other element. Thus, in some embodiments, the atomic concentration of the target element (the dominant element) for defining whether the layer is “heavily” or “lightly” doped is an atomic concentration of a portion of the target element whose function is not compromised. The target element typically consists of one element, but in some embodiments, may consist of two or more elements as long as they have substantially the same characteristics for the intended purpose. In this disclosure, the word “connected” or the like refers to direct or indirect electrical connection, and the word “continuously connected” or the like refers to direct electrical connection without an intervening discrete physical or chemical structure between two structures other than the two structures. In some embodiments, the P− layer (channel) and the P+ layer (isolator) of the select transistor are physically the same layers as the N+ layer and the P− or undoped layer (channel) of the memory transistor, respectively, i.e., two different regions are formed in the same layer except that the region of the select transistor has different dopant concentrations from that in the region of the memory transistor, wherein the P− layer (channel) of the select transistor is continuously connected to the N+ layer of the memory transistor, and the P+ layer of the select transistor is continuously connected to the P− or undoped layer (channel) of the memory transistor.

In some embodiments, the lightly doped P-type semiconductor layers of the select transistors are lightly boron-doped layers formed by doping boron to layers identical to the heavily doped N-type semiconductor layers of the memory transistors, and the heavily doped P-type semiconductor layers of the select transistors are heavily boron-doped layers formed by doping boron to layers identical to the lightly doped or undoped P-type semiconductor layers of the memory transistors. In other embodiments, in place of boron, another trivalent atom such as aluminum can be used. In the above, the P− layer and the P+ layer of the select transistor can be formed using the layers of the memory transistor by doping a trivalent atom such as boron to the layers in a single step.

In some embodiments, the heavily doped N-type semiconductor layers of the memory transistors are heavily phosphorous-doped silicon layers (or doped with arsenic), and the lightly doped or undoped P-type semiconductor layers of the memory transistors are undoped SiGe layers.

In some embodiments, a side of each select transistor opposite to a side connected to the corresponding memory transistor is connected to a bit line or source line, wherein only one select transistor is provided between the bit line or source line and each memory transistor. In the 3D stacked NAND flash memory disclosed in IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 7, JULY 2016, p 866-869, three string select transistors are formed per silicon layer, whereas in the above embodiment, only one select transistor is formed per silicon layer.

In some embodiments, the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to be aligned in the stacking direction. In some embodiments, the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to form a staircase in the longitudinal direction. In some embodiments, a space above the staircase is filled with a heavily doped N-type semiconductor in contact with the staircase, and the heavily doped N-type semiconductor is preferably phosphorous-doped poly-Si.

In another aspect, an embodiment provides a method of fabricating the 3D stacked multilayer semiconductor memory (wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to be aligned in the stacking direction) comprising:

-   -   stacking lightly doped or undoped P-type semiconductor layers         and heavily doped N-type semiconductor layers alternately with         one another in the stacking direction for memory transistors;     -   forming a column using the stacked layers so as to form a         stacked layer structure having a column shape;     -   forming a boron-doped film on the stacked layer structure having         the column shape only in an area where select transistors are to         be formed in the stacking direction, by lithograph and etching;         and     -   annealing the stacked layer structure having the boron-doped         film to thermally remove the boron-doped film while doping boron         to a portion of each lightly doped or undoped P-type         semiconductor layer and a portion of each heavily doped N-type         semiconductor layer where the select transistors are to be         formed, whereby the portion of each lightly doped or undoped         P-type semiconductor layer and the portion of each heavily doped         N-type semiconductor layer are converted to a heavily doped         P-type semiconductor layer and a lightly doped P-type         semiconductor layer of the select transistors, respectively.

In some embodiments, the boron-doped film is constituted by heavily doped boron silicon glass. A silicon glass or silicon oxide is preferred because removal of the layer is readily accomplished, although poly-Si film may be usable. In some embodiments, the lightly doped or undoped P-type semiconductor layers are constituted by undoped SiGe, and the heavily doped N-type semiconductor layers are constituted by heavily phosphorous-doped silicon.

Another embodiment provides a method of fabricating the 3D stacked multilayer semiconductor memory (wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to form a staircase in the longitudinal direction) comprising:

-   -   stacking lightly doped or undoped P-type semiconductor layers         and heavily doped N-type semiconductor layers alternately with         one another in a stacking direction for memory transistors;     -   forming a staircase in the stacked layer structure in a         longitudinal direction by removing a portion of the stacked         layer structure by lithography and etching;     -   doping boron to a portion of the staircase by ion implantation         where select transistors are to be formed, whereby a portion of         each lightly doped or undoped P-type semiconductor layer and a         portion of each heavily doped N-type semiconductor layer         constituting the staircase are converted to a heavily doped         P-type semiconductor layer and a lightly doped P-type         semiconductor layer of the select transistors, respectively; and     -   filling a space formed by removing the portion above the         staircase with a heavily doped N-type semiconductor.

In some embodiments, the lightly doped or undoped P-type semiconductor layers are constituted by undoped SiGe, and the heavily doped N-type semiconductor layers are constituted by heavily phosphorous-doped silicon.

The 3D stacked multilayer semiconductor memory can be produced by any suitable method equivalent to those described in the present disclosure, and a skilled artisan in the art can readily perform such a method in view of the present disclosure, as a matter of routine experimentation.

Embodiments will be explained with reference to the drawings. However, the present invention is not limited to the embodiments.

FIG. 1 illustrates schematic perspective views of a partially fabricated integrated memory array, showing boron-doping processes (a) and (b) according to an embodiment of the present invention. According to this embodiment, produced is a 3D stacked multilayer semiconductor memory wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to be aligned in the stacking direction. Such a method of fabricating the 3D stacked multilayer semiconductor memory comprises: (i) stacking SiGe (undoped) layers 1 and heavily phosphorus-doped Si layers 2 alternately with one another in the stacking direction for memory transistors; (ii) forming columns 6 using the stacked layers so as to each form a stacked layer structure having a column shape; (iii) forming a heavily doped BSG film 3 on the stacked layer structure 6 having the column shape only in an area 7 where select transistors are to be formed in the stacking direction, by lithograph and etching as illustrated in (a) in FIG. 1; and (iv) annealing the stacked layer structure 6 having the heavily doped BSG film to thermally remove the BSG film while doping boron to a portion 7 of the SiGe layers 1 and a portion of the heavily phosphorus-doped Si layers 2 where the select transistors are to be formed, whereby the portion of the SiGe layers 1 and the portion of the heavily phosphorus-doped Si layers 2 are converted to heavily boron-doped layers 4 and lightly boron-doped layers 5 of the select transistors, respectively, as illustrated in (b) in FIG. 1.

When the select transistors are arranged to be aligned in the stacking direction as shown in FIG. 1, a bit line is connected to each heavily phosphorus-doped Si layer as compared with the select transistors arranged using a staircase as illustrated in FIG. 2, which select transistors require one shared bit line.

Further, according to the doping process illustrated in FIG. 1, since the boron-doped film can be deposited in any desired area, the select transistors can be arranged using a staircase so that a single shared bit line can be used.

FIG. 2 illustrates schematic perspective views of a partially fabricated integrated array, showing boron-doping processes (a) to (c) and wiring processes (d) and (e) according to an embodiment of the present invention. According to this embodiment, produced is a 3D stacked multilayer semiconductor memory wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to form a staircase in the longitudinal direction. Such a method of fabricating the 3D stacked multilayer semiconductor memory comprises: (i) stacking undoped layers 11 and N+ layers 12 alternately with one another in the stacking direction for memory transistors; (ii) forming a staircase in the stacked layer structure in the longitudinal direction by removing a portion of the stacked layer structure by lithography and etching as illustrated in (a) in FIG. 2; (iii) doping boron to a portion of the staircase by ion implantation where select transistors are to be formed, whereby a portion of each undoped layer 11 and a portion of each N+ layer 12 constituting the staircase are converted to a P+ layer 13 and a P− layer 14 of the select transistors, respectively, as illustrated in (b) in FIG. 2; (iv) filling a space formed by removing the portion above the staircase with a N+ semiconductor (phosphorous-doped poly-Si) as illustrated in (c) in FIG. 2; (v) forming gate electrodes 16 in a region of the line select transistors (LST) and in a region of word line transistors (WL) by lithography and etching as illustrated in (d) in FIG. 2; and (vi) forming a bit line 17 connected to the line select transistors.

FIG. 3 illustrates schematic perspective views of the partially fabricated integrated array illustrated in FIG. 2, showing array-forming processes (a) to (d) according to an embodiment of the present invention. This process flow comprises: (i) stacking SiGe layers 21 and N+ layers 22 alternately by epitaxial deposition on a substrate 20 having a shallow trench isolation (STI) in which an insulation film such as silicon oxide is filled; (ii) forming a staircase on two sides by etching; (iii) doping boron to the staircase by ion implantation to convert the SiGe layers 21 to P+ layers 23 and the N+ layers 22 to P− layers 24; (iv) filling a space above the staircase with silicon oxide 25 as illustrated in (a) in FIG. 3; (v) removing a portion of the staircase fill 25 by etching; (vi) filling a space above the staircase with N+ poly-Si 26 as illustrated in (b) in FIG. 3; (vii) forming slits by lithography and etching to form columns 27 as illustrated in (c) in FIG. 3; (viii) forming gate electrodes 30 in a region of line select transistors 32 including a cut-off transistor 31, in a region of word line transistors 33, and in a region of cut-off transistors 34 including a source select transistor 35 as illustrated in (d) in FIG. 3; and (ix) forming a bit line 28 and a source line 29 as illustrated in (d) in FIG. 3.

In (d) in FIG. 3, the select transistors are constituted by the cut-off transistor 31, the line select transistors 33, the cut-off transistors 34 (also referred to as source select transistors), and the source select transistor 35. The cut-off transistors 31 and 34 control an ON/OFF state of the line select transistors 32 by setting the gate voltage low. The cut-off transistor 31 is connected to the bit line and is used to select the bottom N+ layer, whereas the source select transistor 35 is connected to the source line (ground) and is used to select the bottom N+ layer, wherein since the bottom N+ layer is required to be connected to the ground, the source select transistor 35 is ON (high voltage), and the cut-off transistor 31 is OFF (low voltage). The cut-off transistors 34 are normally OFF (low voltage), and at a writing mode, the cut-off transistors 34 set high the gate voltage of the line select transistor connected to the selected bit line.

FIG. 4 illustrates a schematic perspective view of fabricated integrated arrays according to an embodiment of the present invention, which correspond to the structures illustrated in (d) in FIG. 3. Each gate electrode 40 is formed to extend over the columns as a common gate electrode. The source line (ground) 39 (M0) is typically formed of tungsten wiring, the bit line 38 (M1) is typically formed of copper wiring, and the word line 41 (M2) is typically formed of copper wiring. Since there are three wiring layers (which correspond to M0, M1, and M2), this configuration has three level interconnects, which is normally attached to a bonding pad made of aluminum (not shown). Although this drawing shows only two M2s, there are 10 M2s corresponding to the gate electrodes (there are 10 gate electrodes in this drawing). Further, this drawing shows only two word lines for convenience of explanation; however, the number of word lines varies depending on the bit number, and typically there are word lines on the mega order in a memory. In the drawing, “WL+LST (2×stacking #)” means that the number of lines is a sum of the number of word lines which normally corresponds to the number of bits, and the number of line select transistors which is the number of stackings multiplied by two (since a region of line select transistors is placed on each of the bit line side and the source line side. The number of stackings is normally 48 or more.

The 3D stacked multilayer semiconductor memory illustrated in FIG. 4 has a wiring structure which is substantially the same as that of 3D NAND flash memory, and thus, no additional area or no additional interconnect wiring is required as compared with 3D NAND flash memory.

FIG. 5 illustrates a schematic equivalent circuit of a fabricated 3D stacked multilayer semiconductor memory, showing writing operation according to an embodiment of the present invention. This circuit is an approximate representation of basic writing operation of the 3D stacked multilayer semiconductor memory illustrated in FIG. 4. Some lines are indicated in bold and some lines are omitted for convenience of explanation. In this circuit, the select transistors are oriented in a horizontal direction, the word line transistors are oriented in a vertical direction, and they are connected in a horizontal direction in each array and between arrays. Source select transistors 1 and 2 (SSL 1, SSL 2) are ON (“H”) only for pre-charging the lines, and after pre-charging, the source select transistors are OFF (“L”), and then, line select transistors (LST1, LST2) and a word line 1 (WL1) are ON (“H”). A source select transistor 3 (SST3) is OFF, and a line select transistor 3 (LST3) is OFF. In this drawing, a transistor 1 (TR1) is selected because all of LST1, LS2, WL1, and a bit line 1 (BL1) are selected. As a result, electron injection from the substrate to the gate of TR1 occurs, thereby accomplishing writing operation. A transistor 2 (TR2) is not selected because although LST1, LS2, and BL1 are selected, a word line 2 (WL2) is not selected. A transistor 3 (TR3) is not selected because although LST1, LS2, and WL1 are selected, a bit line 2 (BL2) is not selected. At TR2 and TR3, no current flow occurs.

FIG. 6 illustrates a schematic equivalent circuit of a fabricated 3D stacked multilayer semiconductor memory, showing reading operation according to an embodiment of the present invention. This circuit corresponds to that shown in FIG. 5. In this drawing, TR1 is selected because all of LST1, LS2, WL1, and BL1 are selected. As a result, current flow occurs at TR 1, thereby accomplishing reading operation. TR2 is not selected because although LST1, LS2, and BL1 are selected, WL2 is not selected. TR3 is not selected because although LST1, LS2, and WL1 are selected, BL2 is not selected. At TR2 and TR3, no current flow occurs.

According to some embodiments of the present invention, single-crystalline channels are used, in place of polycrystalline Si, thereby obtaining high reading speed. According to some embodiments of the present invention, there is no packing density disadvantage as compared with conventional 3D NAND flash memories, and there is a great packing density advantage as compared with planar NOR memories. According to some embodiments of the present invention, the 3D stacked memory is produced by simple processes, e.g., no staircase landing contact, no epitaxial speed control, no deep source contact, etc. are required. Further, according to some embodiments, the 3D stacked memory is produced using the process/equipment established for 3D NAND flash memories. In some embodiments of the present invention, the 3D stacked memory is suitably used as a storage class memory (SCM).

EXAMPLES

In the following examples where conditions and/or structures are not specified, a skilled artisan in the art can readily provide such conditions and/or structures, in view of the present disclosure, as a matter of routine experimentation. Also, in the following examples, the numbers defining the structures and process conditions can be modified by a range of at least ±50% in some embodiments, and such modification can be accomplished readily by the skilled artisan in the art based on routine experimentation in view of the present disclosure. Further, the ranges specified below may include or exclude the lower and/or upper endpoints.

Example 1

Undoped Si (or undoped SiGe) layers and phosphorous-doped Si layers were alternately deposited by epitaxial grow processes on a semiconductor substrate wherein the number of stacked layers was about 64. The thickness of the undoped Si (or undoped SiGe) layer was about 50 nm (typically 45 nm to 55 nm) and the thickness of the phosphorous-doped Si layer was about 20 nm (typically 15 nm to 25 nm).

A staircase was formed in the stacked structure on one side of the stacked structure by patterning, wherein each step of the staircase was constituted by the undoped Si (or undoped SiGe) layer and the phosphorous-doped Si layer. The staircase was formed by: (i) forming a mask (e.g., resist film) in a pattern on the stacked structure of the undoped Si (or undoped SiGe) layers and phosphorous-doped Si layers; (ii) etching the uppermost phosphorous-doped Si layer and undoped Si (or undoped SiGe) layer using the mask to form a step; (iii) etching the mask for next step formation by isotropic etching; (iv) etching the uppermost phosphorous-doped Si layer and undoped Si (or undoped SiGe) layer and the step(s) formed in the previous process using the mask so as to form steps; and (v) repeating processes (iii) and (iv) until the complete staircase constituted by the phosphorous-doped Si layers and undoped Si (or undoped SiGe) layers was formed.

Next, lines (columns) were formed in the staircase-shaped stacked structure. The width of each line and the distance between the lines were both about 40 nm (typically 35 nm to 45 nm). A boron-doped silicon glass (BSG) film was deposited at a thickness of about 10 nm (typically 8 nm to 12 nm) on the stacked structure, followed by removing the BSG film except areas for forming line select transistors (LSTs) by lithography and etching (wherein the areas for forming LSTs oriented in a vertical direction were defined as illustrated in FIG. 1, and the areas for forming LSTs oriented in a horizontal direction were defined along the staircase such as those illustrated in (b) in FIG. 2 except that the areas were set apart from the edges of the staircase). The boron concentration of the BSG film was about 1×10²⁰/cm³ (typically 5×10¹⁹ to 5×10²⁰/cm³). Thereafter, the stacked structure was annealed at a temperature of about 1,000° C. (typically 950° C. to 1050° C.) to disperse boron from the BSG film to the phosphorous-doped Si layers and undoped Si (or undoped SiGe) layers, thereby doping boron to the layers for forming LSTs. After annealing, the BSG film was purposely removed.

Next, a silicon oxide film, a silicon nitride film, and silicon oxide film were deposited each at a thickness of about 5 nm (typically 4 nm to 6 nm) by CVD, and poly-Si was deposited at a thickness of about 30 nm (typically 25 nm to 35 nm), followed by forming word lines (WLs) and line select transistors (LSTs) by patterning. The WLs were formed in the vertical direction, i.e., perpendicular to the stacking direction, and the LSTs were formed along the line pattern of each doped layer (covering the doped layers) along the staircase on the staircase side and vertically on the side having no staircase. The poly-Si was completely removed from each space between the WLs and the LSTs.

Next, a first interconnect insulation film was formed on the staircase of the stacked structure, and a first contact was formed by forming a hole and filling the hole with tungsten, and then, a shared bit line (BL) was formed. Next, a second interconnect insulation film was formed on the side having no staircase of the stacked structure, and a second contact was formed for each select transistor by forming a hole and filling the hole with tungsten, and then, an unshared select line (SL) was formed for each select transistor.

In the above, the staircase was formed on the bit line side of the stacked structure, and no staircase was formed on the source line side of the stacked structure;

however, the sides can be reversed, and both sides can have staircases, or both sides can have no staircase.

Example 2

In Example 2, the staircase was formed on both sides of the stacked structure in the same manner as described in Example 1. Next, boron was doped to each staircase constituted by the phosphorous-doped Si layers and undoped Si (or undoped SiGe) layers by ion implantation at a boron concentration of 1×10¹⁶/cm² (typically 5×10¹⁵/cm² to 5×10¹⁶/cm²). Next, the stacked structure was annealed at a temperature of about 1,000° C. (typically 950° C. to 1050° C.) to disperse boron in the phosphorous-doped Si layers and undoped Si (or undoped SiGe) layers.

Next, a silicon oxide film was deposited on the entire surfaces of the stacked structure with the staircases by CVD, followed by flattening the surface by CMP whereby the space above the staircases was filled with the silicon oxide film as illustrated in (a) in FIG. 3. Next, the silicon oxide film was removed from the space above the staircases by lithography and etching, and then, phosphorous-doped poly-Si was deposited by CVD on the staircase, followed by flattening the surface by CMP, whereby only the space above the staircase was filled with the phosphorous-doped poly-Si as illustrated in (b) in FIG. 3. The phosphorous concentration of the phosphorous-doped poly-Si was about 1×10²⁰/cm³ (typically 5×10¹⁹ to 5×10²⁰/cm³).

Next, slits were formed in the stacked structure by lithography and etching as illustrated in (c) in FIG. 3. The width of each slit and the width of each line (the remaining portion between adjacent slits) were both about 40 nm (typically 35 nm to 45 nm).

Next, a silicon oxide film, a silicon nitride film, and silicon oxide film were deposited each at a thickness of about 5 nm (typically 4 nm to 6 nm) by CVD, and poly-Si was deposited at a thickness of about 30 nm (typically 25 nm to 35 nm), followed by forming word lines (WLs) and line select transistors (LSTs) by patterning. The WLs and the LSTs were both formed in the vertical direction, i.e., perpendicular to the stacking direction as illustrated in (d) in FIG. 3. The poly-Si was completely removed from each space between the WLs and the LSTs.

Next, a first interconnect insulation film was formed, and then, a first contact was formed on the phosphorous-doped poly-Si by forming a hole and filling the hole with tungsten, and then, a shared source line (SL) was formed as illustrated in (d) in FIG. 3 or FIG. 4. Next, a second interconnect insulation film was formed, and then, a second contact was formed on the phosphorous-doped poly-Si by forming a hole and filling the hole with tungsten, and then, a shared bit line (BL) was formed as illustrated in (d) in FIG. 3 or FIG. 4. Next, a third interconnect insulation film was formed, and a third contact was formed on the word lines formed of poly-Si, and then connected to a low resistance wiring as illustrated in FIG. 4. The wiring was constituted by tungsten or copper. Lastly, after forming another interconnect insulation film, the columns were attached to an aluminum bonding pad.

It will be understood by those of skill in the art that numerous and various modifications can be made without departing from the spirit of the present invention. Therefore, it should be clearly understood that the forms of the present invention are illustrative only and are not intended to limit the scope of the present invention. 

1. 3D stacked multilayer semiconductor memory comprising: memory transistors constituted by heavily doped N-type semiconductor layers and lightly doped or undoped P-type semiconductor layers alternately layered with one another in a stacking direction, each layer extending in a longitudinal direction perpendicular to the stacking direction; and select transistors constituted by lightly doped P-type semiconductor layers and heavily doped P-type semiconductor layers alternately layered with one another, said select transistors being provided with gate electrodes, wherein the lightly doped P-type semiconductor layers of the select transistors are connected, continuously in the longitudinal direction, to one ends of the heavily doped N-type semiconductor layers of the memory transistors, respectively, and the heavily doped P-type semiconductor layers of the select transistors are connected, continuously in the longitudinal direction, to one ends of the lightly doped or undoped P-type semiconductor layers of the memory transistors, respectively, and wherein the lightly doped P-type semiconductor layers of the select transistor function as channels to select one of the heavily doped N-type semiconductor layers when applying voltage to the gate electrodes, and the heavily doped P-type semiconductor layers of the select transistors function as isolators to isolate the heavily doped P-type semiconductor layers from the lightly doped or undoped P-type semiconductor layers of the memory transistors.
 2. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the lightly doped P-type semiconductor layers of the select transistors are lightly boron-doped layers formed by doping boron to layers identical to the heavily doped N-type semiconductor layers of the memory transistors, and the heavily doped P-type semiconductor layers of the select transistors are heavily boron-doped layers formed by doping boron to layers identical to the lightly doped or undoped P-type semiconductor layers of the memory transistors.
 3. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the heavily doped N-type semiconductor layers of the memory transistors are heavily phosphorous-doped silicon layers, and the lightly doped or undoped P-type semiconductor layers of the memory transistors are undoped SiGe layers.
 4. The 3D stacked multilayer semiconductor memory according to claim 1, wherein a side of each select transistor opposite to a side connected to the corresponding memory transistor is connected to a bit line or source line, wherein only one select transistor is provided between the bit line or source line and each memory transistor.
 5. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer, and the underlying heavily doped P-type semiconductor layer, are arranged so as to be aligned in the stacking direction.
 6. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to form a staircase in the longitudinal direction.
 7. The 3D stacked multilayer semiconductor memory according to claim 6, wherein a space above the staircase is filled with a heavily doped N-type semiconductor in contact with the staircase.
 8. The 3D stacked multilayer semiconductor memory according to claim 7, wherein the heavily doped N-type semiconductor is phosphorous-doped poly-Si.
 9. A method of fabricating the 3D stacked multilayer semiconductor memory of claim 5, comprising: stacking lightly doped or undoped P-type semiconductor layers and heavily doped N-type semiconductor layers alternately with one another in the stacking direction for memory transistors; forming a column using the stacked layers so as to form a stacked layer structure having a column shape; forming a boron-doped film on the stacked layer structure having the column shape only in an area where select transistors are to be formed in the stacking direction, by lithograph and etching; and annealing the stacked layer structure having the boron-doped film to thermally remove the boron-doped film while doping boron to a portion of each lightly doped or undoped P-type semiconductor layer and a portion of each heavily doped N-type semiconductor layer where the select transistors are to be formed, whereby the portion of each lightly doped or undoped P-type semiconductor layer and the portion of each heavily doped N-type semiconductor layer are converted to a heavily doped P-type semiconductor layer and a lightly doped P-type semiconductor layer of the select transistors, respectively.
 10. The method according to claim 9, wherein the boron-doped film is constituted by heavily doped boron silicon glass.
 11. The method according to claim 10, wherein the lightly doped or undoped Ptype semiconductor layers are constituted by undoped SiGe, and the heavily doped N-type semiconductor layers are constituted by heavily phosphorous-doped silicon.
 12. A method of fabricating the 3D stacked multilayer semiconductor memory of claim 7, comprising: stacking lightly doped or undoped P-type semiconductor layers and heavily doped N-type semiconductor layers alternately with one another in a stacking direction for memory transistors; forming a staircase in the stacked layer structure in a longitudinal direction by removing a portion of the stacked layer structure by lithography and etching; doping boron to a portion of the staircase by ion implantation where select transistors are to be formed, whereby a portion of each lightly doped or undoped Ptype semiconductor layer and a portion of each heavily doped N-type semiconductor layer constituting the staircase are converted to a heavily doped P-type semiconductor layer and a lightly doped P-type semiconductor layer of the select transistors, respectively; and filling a space formed by removing the portion above the staircase with a heavily doped N-type semiconductor.
 13. The method according to claim 12, wherein the lightly doped or undoped Ptype semiconductor layers are constituted by undoped SiGe, and the heavily doped N-type semiconductor layers are constituted by heavily phosphorous-doped silicon. 